1. Field of the Invention
The present invention relates to a semiconductor memory and a method of fabrication thereof. More particularly, the invention relates to improvements of data storage nodes in a semiconductor memory.
2. Background Art
FIGS. 5A through 5D illustrate the structure and operation of a conventional semiconductor memory device. FIG. 5A is a cross-sectional view of a semiconductor memory device. In FIG. 5A, Q1 and Q2 indicate MOS transistors and ND represents a data storage node. In this semiconductor memory device, a P-type well 2 on a silicon substrate 1 is isolated by a field isolation oxide film 3. On the surface of the film 3 are a gate oxide film 4, a gate electrode 5 and a gate side wall 6.
A source-drain region SD1 of the MOS transistor Q1 comprises an N- region 7 and an N+ region 9. A source-drain region SD2 of the MOS transistor Q2 includes an N- region 8 and an N+ region 9. The data storage node ND has an N- region 8 forming an N-/P junction with the P-type well 2. The N- region 8 of the MOS transistor Q2 and the N- region 8 of the data storage node ND are formed at the same time and have the same impurity profile.
FIGS. 6A through 6C illustrate how the conventional semiconductor memory device of FIG. 5A is fabricated. As shown in FIG. 6A, the field isolation oxide film 3 is first formed over the P-type well 2 of the silicon substrate 1. The gate oxide film 4 and gate electrode 5 are then formed in regions where the MOS transistors Q1 and Q2 are to be fabricated. The regions of the MOS transistor Q2 and data storage node ND are covered with a resist 11a. Phosphorus (P) ions are implanted into the region of the MOS transistor Q1 to form the N- region 7.
As shown in FIG. 6B, the region of the MOS transistor Q1 is covered with a resist 11b. Arsenic (As) ions are implanted into the region of the MOS transistor Q2 and into the region of the data storage node ND to form the N- regions 8 for those respective components. Then, as illustrated in FIG. 6C, the side wall 6 is formed for the gate electrode 5. The region of the data storage node ND is covered with a resist 11c. Arsenic (As) ions are implanted into the regions of the MOS transistors Q1 and Q2 to form the N+ regions 9 for those respective components. The N+ regions 9 are formed deep in the substrate through high-level energy injection and by implantation of high-density arsenic ions. The semiconductor memory device shown in FIG. 5A is fabricated by the above process.
In a conventional semiconductor memory device having the structure outlined above, PN junctions in the data storage node ND and other portions of the device having the same potential level [as shown in FIG. 6B] are formed at the same time as the N- region 8 of the nearby N-channel MOS transistor Q2 and implanted with the same type of ions.
Thus, the densities and profile of the impurities in the N- region 8 are determined predominantly by the performance of the MOS transistor Q2. This poses a problem in that the performance of the N- region 8 is not necessarily adequate when used for data storage node ND. Specifically, its PN junction characteristics tend to include a leak current component.
FIGS. 5B and 5C are cross sectional views showing typical densities and profiles of P- and N-type impurities in the PN junction of the data storage node ND of FIG. SA as well as depletion layers associated therewith. FIG. 5B illustrates a depletion layer in effect when no bias voltage is applied, and FIG. 5C indicates a deletion layer in effect when a bias voltage of 3 V is applied. Because the densities and profiles of P- and N-type impurities in the PN junction are insufficient, bias voltages higher than a certain level (2.5 V in this example) cause the depletion layer to extend to the substrate surface and to provide a leak path, as shown in FIG. 5C. This leads to generation of a leak current component in the PN junction characteristics as shown graphically in FIG. 5D. The leak current can increase up to about ten times the magnitude of its normal state.